1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a fabrication method for a metal oxide semiconductor field effect transistor (MOSFET) device capable of settling deterioration of short channel effect (SCE) due to decrease in critical size of gates and preventing junction leakage from occurring in a junction region between ion regions.
2. Discussion of the Background
FIGS. 1A to 1D sequentially illustrate a conventional fabrication method for a MOSFET device.
In FIG. 1A, a buffer oxide film 11 is formed on an upper surface of a semiconductor substrate 10, a nitride film 13 is formed on the buffer oxide film 11 and a channel region 14 is formed by implanting impurities into an opened area of the semiconductor substrate 10.
In an N-channel MOSFET (hereinafter, called NMOSFET), the semiconductor substrate 10 is P-type, and in a P-channel MOSFET (hereinafter, called PMOSFET), the substrate 10 is N-type, i.e., the impurities are P-type in NMOSFET and N-type in PMOSFET. Further, the channel region 14 defines a threshold voltage.
As shown in FIG. 1B, after removing the nitride film 13 and the buffer oxide film 11, a gate oxide film 15 and a polysilicon film 16 are sequentially formed on the semiconductor substrate 10. A photoresist pattern 17 is formed on the polysilicon film 16 and, with the photoresist pattern 17 as a mask, N.sup.+ -type ions in case of MOSFET (or P.sup.+ -type ions in PMOSFET) are implanted into the polysilicon film 16 (polysilicon doping). Here, when forming the photoresist pattern 17, an upper surface of a portion of the polysilicon film 16 above the channel region 14 is opened.
As shown in FIG. 1C, the photoresist pattern 17 is removed and the polysilicon film 16 is patterned, thus forming a gate 18. With the gate 18 as a mask, low-concentration ions (NMOS: n-, PMOS: p -) are implanted into the semiconductor substrate 10, thus a lightly-doped-drain (LDD) ion region 19 is formed at each side of the channel region 4 in the semiconductor substrate 10.
As shown in FIG. 1D, a side wall 20 is formed at both sides of the gate 18. Finally, high-concentration ions (NMOS: n+, PMOS: p+) and opposite-type ions thereof (NMOS: p+, PMOS: n+) are sequentially implanted into the semiconductor substrate 10, for thus forming a source/drain region 21 and a halo-type ion implantation region 22, respectively.
However, the conventional fabrication method for the MOSFET device has some problems.
First, as the size of the semiconductor devices decrease the critical size of gates should also decrease. This reduction of critical size may cause a short channel effect (SCE) to occur leading to poor quality devices.
Second, to alleviate the above problem, the halo ion region 22 has the opposite type of the source/drain region 21. However, due to the excessive concentration difference between the source/drain region 21 and the halo ion region 22, junction leakage can occur in a junction region between the two regions 21, 22.